View IBMB6M64734BGA_4863649.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 23 features ? 184-pin registered 8-byte dual in-line memory module ? 64mx72 double data rate (ddr) sdram dimm (64m x 4 sdram s ) ? performance: ? intended for 100 mhz applications ? inputs and outputs are sstl-2 compatible ?v dd = 2.5volt 0.2, v ddq = 2.5volt 0.2 ? single pulsed ras interface ? sdrams have four internal banks for concur- rent operation ? module has one physical bank ? bi-directional data strobe with one clock cycle preamble and one-half clock post-amble ? differential clock inputs ? data is read or written on both clock edges ? address and control signals are fully synchro- nous to positive clock edge ? programmable operation: - dimm cas latency: 3, 3.5 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? power down mode ? 13/11/2 addressing (row/column/bank) ? 7.8 m s max. average periodic refresh interval ? card size: 5.25" x 0.157" x 1.70" ? gold contacts ? sdram s in 66-pin tsop-ii package ? serial presence detect description IBMB6M64734BGA is a registered 184-pin double data rate (ddr) synchronous dram dual in-line memory module (dimm), organized as a one-bank high-speed memory array. the 64mx72 module is a single-bank dimm that uses eighteen 64mx4 ddr sdrams in 400 mil tsop packages. this dimm achieves high-speed data transfer rates of up to 200 mhz. the dimm is intended for use in applications oper- ating from 100 mhz to 125 mhz clock speeds with data rates of 200 to 250 mhz. all control and address signals are re-driven through registers to the ddr sdram devices. the control and address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge. a phase-locked loop (pll) on the dimm is used to re-drive the differential clock signals to both the ddr sdram devices and the registers, thus mini- mizing system clock loading. clock enable (cke0) controls all devices on the dimm. prior to any access operation, the device cas latency and burst type/length/operation type must be programmed into the dimm by address inputs a0-a12 and i/o inputs ba0 and ba1 using the mode register set cycle. the dimm cas latency exceeds the sdram device specification by one clock due to the address and control signals being clocked to the sdram devices. these dimms are manufactured using raw cards developed for broad industry use by ibm as refer- ence designs. the use of these common design files will minimize electrical variation between sup- pliers. the dimm uses serial presence detects imple- mented via a serial eeprom using the two-pin iic protocol. the first 128 bytes of serial pd data are programmed and locked during module assembly. the last 128 bytes are available to the customer. all ibm 184 ddr sdram dimms provide a high- performance, flexible 8-byte interface in a 5.25 long space-saving footprint. pc1600 units dimm cas latency 3 3.5 f ck clock frequency 100 125 mhz t ck clock cycle 10 8.0 ns f dq dq burst frequency 200 250 mhz .
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 23 06k6597.h02812a 1/01 card outline pin description ck0, ck0 differential clock inputs dq0 - dq63 data input/output cke0 clock enable cb0 - cb7 check bit data input/output ras row address strobe dqs0-dqs17 bidirectional data strobes cas column address strobe v dd power (2.5v) we write enable v ddq supply voltage for dqs (2.5v) s0 chip select v ss ground a0 - a9, a11, a12 address inputs nc no connect a10/ap address input/autoprecharge scl serial presence detect clock input ba0, ba1 sdram bank address inputs sda serial presence detect data input/output reset reset pin sa0-sa2 serial presence detect address inputs v ref reference voltage for sstl_2 inputs v ddspd serial eeprom positive power supply (2.5 v) 1 93 52 144 53 145 92 184 (front) (back)
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 23 184-pin ddr sdram dimm pin assignments front side (left side 1 - 52, right side 53 - 92) back side (left side 93 -144, right side 145 -184) pin # x72 ecc pin # x72 ecc pin # x72 ecc pin # x72 ecc 1 vref 48 a0 93 vss 140 dqs17 2 dq0 49 cb2 94 dq4 141 a10 3 vss 50 vss 95 dq5 142 cb6 4 dq1 51 cb3 96 vddq 143 vddq 5 dqs0 52 ba1 97 dsq9 144 cb7 6 dq2 key 98 dq6 key 7 vdd 53 dq32 99 dq7 145 vss 8 dq3 54 vddq 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 reset 56 dqs4 102 nc 148 vdd 11 vss 57 dq34 103 nc 149 dqs13 12 dq8 58 vss 104 vddq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vddq 61 dq40 107 dqs10 153 dq44 16 nc 62 vddq 108 vdd 154 ras 17 nc 63 we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vddq 19 dq10 65 cas 111 nc 157 s0 20 dq11 66 vss 112 vddq 158 nc 21 cke0 67 dqs5 113 ba2 159 dqs14 22 vddq 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 vdd 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vddq 27 a9 73 dq49 119 dqs11 165 dq52 28 dq18 74 vss 120 vdd 166 dq53 29 a7 75 nc 121 dq22 167 nc 30 vddq 76 nc 122 a8 168 vdd 31 dq19 77 vddq 123 dq23 169 dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vddq 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vddid 128 vddq 174 dq60 37 a4 83 dq56 129 dqs12 175 dq61 38 vdd 84 dq57 130 a3 176 vss 39 dq26 85 vdd 131 dq30 177 dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 vss 88 dq59 134 cb4 180 vddq 43 a1 89 vss 135 cb5 181 sa0 44 cb0 90 nc 136 vddq 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 vdd 92 scl 138 ck0 184 vddspd 47 dqs8 139 vss nc = no connect; nu = not useable; du = do not use ordering information part number organization speed sdram cas latency leads dimension power v dd /v ddq IBMB6M64734BGA - 8nt 64mx72 pc1600 3 gold 5.25" x 1.7" x 0.157" 2.5 v/2.5 v
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 23 06k6597.h02812a 1/01 64x72 ecc ddr registered sdram dimm block diagram (1 bank, x4 ddr sdrams) rs0 dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cb0 cb1 cb2 cb3 dqs d8 cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs vss dqs1 dqs3 dqs8 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 dm8/dqs17 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/ cs relationships are maintained as shown. 3. dq/dqs resistors are 22 ohms. 4. vddid strap connections (for memory device vdd,vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. address and control resistors are 22 ohms. v dd v ss d0-d17 d0-d17 v ddq d0-d17 d0-d17 vref v ddid strap: see note 4 ck0, ck0 --------- pll* * wire per clock loading table/wiring diagrams ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a11 ra0-ra11 -> a0-a11: sdrams d0-d17 ras rras -> ras: sdrams d0-d17 s0 rs0 -> cs: sdrams d0-d17 cas rcas -> cas: sdrams d0-d17 cke0 rcke0a -> cke: sdrams d0-d17 we rwe -> we: sdrams d0-d17 r e g i s t e r pck pck reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 23 input/output functional description symbol type polarity function ck0 (sstl) positive edge the positive line of the differential pair of system clock inputs which drives the input to the on- dimm pll. all the ddr sdram address and control inputs are sampled on the rising edge of their associated clocks. ck0 (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on- dimm pll. cke0 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deacti- vating the clocks, cke low initiates the power down mode, or the self refresh mode. s0 (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas, we (sstl) active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-2 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0,1 (sstl) selects which sdram bank of four is activated. a0 - a9, a11, a12, a10/ap (sstl) during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-a9, a11 defines the column address (ca0-ca10) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autopre- charge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, autopre- charge is disabled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1. if ap is low, ba0 and ba1 are used to define which bank to precharge. dq0 - dq63, cb0 - cb7 (sstl) data and check bit input/output pins. check bits are only applicable on the x72 dimm config- urations. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic dqs0-dqs17 (sstl) negative and positive edge data strobe for input and output data reset (lvc- mos) active low asynchronously forces all register outputs low when reset is low. this signal can be used during power up to ensure cke0 and cke1 are low and sdram dqss are hi-z. sa0 - 2 these signals are tied at the system planar to either v ss or v dd to configure the serial spd eeprom address range. sda this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup. scl this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v dd to act as a pullup. v ddspd supply serial eeprom positive power supply.
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 23 06k6597.h02812a 1/01 : serial presence detect (part 1 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram ddr 07 3 number of row addresses on assembly 13 0d 4 number of column addresses on assembly 11 0b 5 number of physical banks on dimm 1 01 6-7 data width of assembly x72 4800 8 voltage interface level of this assembly sstl 2.5v 04 9 sdram device cycle time at maximum cl (clx = 2.5) 8.0ns 80 1 10 sdram device access time from clock at cl=2.5 0.8ns 80 11 dimm configuration type ecc 02 12 refresh rate/type 7.8 m s/sr 82 13 primary sdram device width x4 04 14 error checking sdram device width x4 04 15 sdram device attributes: minimum clock delay, random column access 1 clock 01 16 sdram device attributes: burst lengths supported 2, 4, 8 0e 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latency 2, 2.5 0c 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 1 02 21 sdram module attributes registered with pll, differential clock 26 22 sdram device attributes: general v dd 0.2v 80 23 minimum clock cycle at clx-0.5 (cl = 2) 10.0ns a0 1 24 maximum data access time (t ac ) from clock at clx-0.5 (cl = 2) 0.8ns 80 25 minimum clock cycle time at clx-1 (cl = 1.5) n/a 00 26 maximum data access time (t ac ) from clock at clx-1 (cl = 1.5) n/a 00 27 minimum row precharge time (t rp ) 20.0ns 50 28 minimum row active to row active delay (t rrd ) 15.0ns 3c 29 minimum ras to cas delay (t rcd ) 20.0ns 50 30 minimum active to precharge time (t ras ) 50.0ns 32 31 module bank density - 64mx72 512mb 80 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. cc = checksum data byte, 00-ff (hex). 3. r = alphanumeric revision code, a-z, 0-9. 4. rr = ascii coded revision code byte r. 5. ww = binary coded decimal week code, 01-52 (decimal) ? 01-34 (hex). 6. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex). 7. ss = serial number data byte, 00-ff (hex). 8. setup and hold values assume a 1 volt/ns slew rate.
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 23 32 address and command setup time before clock 1.1ns b0 8 33 address and command hold time after clock 1.1ns b0 34 data/data mask input setup time before clock 0.6ns 60 35 data/data mask input hold time after clock 0.6ns 60 36-61 reserved undefined 00 62 spd revision 0 00 63 checksum for bytes 0 - 62 checksum data cc 2 64-71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location xx 73-90 module part number ascii b6m64734bga -8nt 42364d3634373334424741 2d384e54202020 3, 4 91-92 module revision code r plus ascii blank rr20 4 93-94 module manufacturing date year/week code yyww 5, 6 95-98 module serial number serial number ssssssss 7 99-127 reserved undefined 00 128-255 open for customer use undefined 00 serial presence detect (part 2 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. cc = checksum data byte, 00-ff (hex). 3. r = alphanumeric revision code, a-z, 0-9. 4. rr = ascii coded revision code byte r. 5. ww = binary coded decimal week code, 01-52 (decimal) ? 01-34 (hex). 6. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex). 7. ss = serial number data byte, 00-ff (hex). 8. setup and hold values assume a 1 volt/ns slew rate.
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 23 06k6597.h02812a 1/01 absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss - 0.5 to v ddq + 0.5 v v in voltage on inputs relative to v ss sdram device - 0.5 to + 2.7 v serial pd device -0.3 to +6.5 v v dd voltage on v dd supply relative to v ss - 0.5 to + 2.7 v v ddq voltage on v ddq supply relative to v ss - 0.5 to + 2.7 v v ddspd voltage on v ddspd supply relative to v ss - 0.3 to +5.5 v t a operating temperature (ambient) 0 to + 70 c t stg storage temperature (plastic) - 55 to + 150 c p d power dissipation tbd w i out short circuit output current 50 ma note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operat ional sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli ability. capacitance parameter symbol max. units notes input capacitance: ck0, ck0 c i1 7pf1 input capacitance: a0-a12, ba0, ba1, we, ras, cas, cke0, so c i2 7pf1 input capacitance: reset c i3 7pf1 input capacitance: sa0-sa2, scl c i4 9pf1 input/output capacitance: dq0-63, dqs0-17, cb0-7 c io1 10 pf 1, 2 input/output capacitance: sda c io2 11 pf 1. v ddq = v dd = 2.5v 0.2v, f = 100 mhz, t a = 25 c, v out (dc) = v ddq/2 , v out (peak to peak) = 0.2v. 2. dm inputs are grouped with i/o pins re?ecting the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level.
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 23 electrical characteristics and dc operating conditions (0?c t a 70 c; v ddq = 2.5v 0.2v, v dd = + 2.5v 0.2v, see ac characteristics) symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage i/o supply voltage 00v v ref i/o reference voltage 0.49 v ddq 0.51 v ddq v 1, 2 v tt i/o termination voltage (system) v ref - 0.04 v ref + 0.04 v 1, 3 v ddspd supply voltage spd supply voltage 2.3 2.7 v v ih(dc) input high (logic1) voltage dq0-63, cb0-7, dqs0-17 v ref + 0.15 v ddq + 0.3 v1 address and control inputs v ref + 0.18 v ddq + 0.3 reset 1.7 v ddq + 0.3 v il(dc) input low (logic0) voltage dq0-63, cb0-7, dqs0-17 - 0.3 v ref - 0.15 v1 address and control inputs - 0.3 v ref - 0.18 reset - 0.3 0.8 v in(dc) input voltage level, ck and ck inputs - 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.36 v ddq + 0.6 v 1, 4 i i input leakage current any input 0v v in v dd (all other pins not under test = 0v) address and control inputs - 55 m a1 dq0-63, cb0-7, dqs0-17 - 55 ck and ck - 10 10 i oz output leakage current (dqs are disabled; 0v v out v ddq dq0-63, cb0-7, dqs0-17 - 55 m a1 sda - 11 i oh output high current (v out = 1.95v) - 16.8 ma 1 i ol output low current (v out = 0.35v) 16.8 ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to- peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck.
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 23 06k6597.h02812a 1/01 ac characteristics (notes 1-5 apply to the following tables; electrical characteristics and dc operating conditions, ac operating conditions, operating, standby, and refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still ref- erenced to v ref (or to the crossing point for ck, ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuit diagram ac operating conditions (0 ?c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage. dq0-63, cb0-7, dqs0-17 v ref + 0.31 v 1, 2 address and control inputs v ref + 0.35 v il(ac) input low (logic 0) voltage. dq0-63, cb0-7, dqs0-17 v ref - 0.31 v 1, 2 address and control inputs v ref - 0.35 v id(ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix(ac) input differential pair cross point voltage, ck and ck inputs (0.5 v ddq ) - 0.2 (0.5 v ddq ) + 0.2 v 1, 2, 4 f ssc ssc modulation frequency 30 50 khz d ssc 0 -.50 % 1. input slew rate = 1v/ns . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. 50 w timing reference point output (v out ) 30pf v tt
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 23 operating, standby, and refresh currents (0 ?c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) symbol parameter/condition ma notes i dd0 operating current : one logical bank; active / precharge; t rc = t rc min ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2190 1 i dd1 operating current : one bank; active / read / precharge; burst = 2; t rc = t rc min ; cl = 2.5; i out = 0ma; address and control inputs changing once per clock cycle 2460 1 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max 1100 1 i dd2n idle standby current: cs 3 v ih min ; all banks idle; cke 3 v ih min ; address and control inputs changing once per clock cycle 1380 1 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max 1110 1 i dd3n active standby current : one bank; active / precharge; cs 3 v ih min ; cke 3 v ih min ; t rc = t ras max ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1740 1 i dd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; i out = 0ma 3180 1 i dd4w operating current : one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2.5 2910 1 i dd5 auto-refresh current :t rc = t rfc min t rc = 7.8 m s 3720 1, 3 1144 i dd6 self-refresh current : cke 0.2v 61 1, 2 i dd7 operating current : four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc min ; i out = 0ma. tbd 1 1. i dd specifications are valid after the sdrams are properly initialized. 2. enables on-chip refresh and address counters. 3. current at 7.8 m s is time averaged value of i dd5 at t rfc min and i dd2p over 7.8 m s.
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 23 06k6597.h02812a 1/01 electrical characteristics and ac timing - absolute speci?cations (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 1 of 2) symbol parameter pc 1600 unit notes min max t ac dq output access time from ck/ ck - 0.8 + 0.8 ns 1, 2, 3, 4 t dqsck dqs output access time from ck/ ck - 0.8 + 0.8 ns 1, 2, 3, 4 t ch ck high-level width 0.45 0.55 t ck 1, 2, 3, 4 t cl ck low-level width 0.45 0.55 t ck 1, 2, 3, 4 t ck clock cycle time cl = 3.5 8 12 ns 1, 2, 3, 4 cl = 3.0 10 12 ns 1, 2, 3, 4 t dh dq and dm input hold time 0.6 ns 1, 2, 3, 4, 18, 19 t ds dq and dm input setup time 0.6 ns 1, 2, 3, 4, 18, 19 t dipw dq and dm input pulse width (each input) 2 ns 1, 2, 3, 4 t hz data-out high-impedance time from ck/ ck - 0.8 + 0.8 ns 1, 2, 3, 4, 5 t lz data-out low-impedance time from ck/ ck - 0.8 + 0.8 ns 1, 2, 3, 4, 5 t dqsq dqs-dq skew (dqs & associated dq signals) + 0.6 ns 1, 2, 3, 4 t dqsqa dqs-dq skew (dqs & all dq signals) + 0.6 ns 1, 2, 3, 4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time t ch or t cl t ck 1, 2, 3, 4 t qh data output hold time from dqs t hp - 1.0ns t ck 1, 2, 3, 4 t dqss write command to first dqs latching transition 0.75 1.25 t ck 1, 2, 3, 4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 t ck 1, 2, 3, 4 t dss dqs falling edge to ck setup time (write cycle) 0.2 t ck 1, 2, 3, 4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 t ck 1, 2, 3, 4 t mrd mode register set command cycle time 16 ns 1, 2, 3, 4 t wpres write preamble setup time 0 ns 1, 2, 3, 4, 7 t wpst write postamble 0.40 0.60 t ck 1, 2, 3, 4, 6 t wpre write preamble 0.25 t ck 1, 2, 3, 4 t ih address and control input hold time (fast slew rate) 1.1 ns 2, 3, 4, 11, 13, 14 t is address and control input setup time (fast slew rate) 1.1 ns 2, 3, 4, 11, 13, 14 t ih address and control input hold time (slow slew rate) 1.1 ns 2, 3, 4, 12, 13, 14, 17 t is address and control input setup time (slow slew rate) 1.1 ns 2, 3, 4, 12, 13, 14, 17 t ipw input pulse width ns 2, 3, 4, 14 t rpre read preamble 0.9 1.1 t ck 1, 2, 3, 4 t rpst read postamble 0.40 0.60 t ck 1, 2, 3, 4
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 23 t ras active to precharge command 50 120,000 ns 1, 2, 3, 4 t rc active to active/auto-refresh command period 70 ns 1, 2, 3, 4 t rfc auto-refresh to active/auto-refresh command period 80 ns 1, 2, 3, 4 t rcd active to read or write delay 20 ns 1, 2, 3, 4 t rap active to read command with autoprecharge 20 ns 1, 2, 3, 4 t rp precharge command period 20 ns 1, 2, 3, 4 t rrd active bank a to active bank b command 15 ns 1, 2, 3, 4 t wr write recovery time 15 ns 1, 2, 3, 4 t dal auto precharge write recovery + precharge time (t wr ? t ck ) + (t rp ? t ck ) t ck 1, 2, 3, 4, 16 t wtr internal write to read command delay 1 t ck 1, 2, 3, 4 t xsnr exit self-refresh to non-read command 80 ns 1, 2, 3, 4 t xsrd exit self-refresh to read command 200 t ck 1, 2, 3, 4 t refi average periodic refresh interval 7.8 m s 1, 2, 3, 4, 8 t qcs qfc setup time on read 0.9 1.1 t ck 1, 2, 3, 4, 15 t qch qfc hold time on read 0.4 0.6 t ck 1, 2, 3, 4, 15 t qcsw delay from ck edge of write command to qfc low on write 4.0 ns 1, 2, 3, 4, 9, 15 t qchw qfc hold time on write 1.25 2.0 ns 1, 2, 3, 4, 10, 15 electrical characteristics and ac timing - absolute speci?cations (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 2 of 2) symbol parameter pc 1600 unit notes min max
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 23 06k6597.h02812a 1/01 electrical characteristics and ac timing - absolute speci?cations notes 1. input slew rate = 1v/ns. 2. the ck/ ck input reference level (for timing reference to ck/ ck) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck, is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac character- istics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parame- ters are not referred to a speci?c voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the speci?c requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is de?ned as monotonic and meeting the input slew rate speci?cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. qfc is enabled as soon as possible after the rising ck edge that registers the write command. 10. qfc is disabled as soon as possible after the last valid dqs edge transitions low. 11. for command/address input slew rate 3 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 12. for command/address input slew rate 3 0.5v/ns and < 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 13. ck/ ck slew rates are 3 1.0v/ns. 14. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 15. the speci?ed timing is guaranteed assuming qfc is connected to a test load consisting of 20pf to ground and a pull up resistor of 150 ohms to v ddq . 16. for each of the terms in parentheses, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. (notes continue on the following page.)
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 23 17. an input setup and hold time derating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. 18. an input setup and hold time derating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. 19. an i/o delta rise, fall derating table is used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ. input slew rate d t is d t ih unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns + 50 0 ps 1, 2 0.3 v/ns + 100 0 ps 1, 2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. input slew rate d t ds d t dh unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns + 75 + 75 ps 1, 2 0.3 v/ns + 150 + 150 ps 1, 2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. delta rise and fall rate d t ds d t dh unit note 0.0 ns/v 0 0 ps 1, 2, 3, 4 0.25 ns/v + 50 + 50 ps 1, 2, 3, 4 0.5 ns/v + 100 + 100 ps 1, 2, 3, 4 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = -0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 23 06k6597.h02812a 1/01 wiring and topology this section contains the information needed to understand the timing relationships presented in the ac characteristics section. because the system designer must measure all signals at the first receiving device (sdram dq pin for data, register input pin for address and controls, and pll check input pin for clock), the following pages provide detailed information on these inputs. in some cases dimm timing adjustments are listed in the specifications, and in some cases it is recommended that the customer determine this informa- tion via simulation. this section enables the customer to understand the device pinouts on the dimm, the net structures, and the loading associated with these devices. for detailed timing analysis, contact an ibm mar- keting representative for simulation models. system-level modeling is strongly recommended to determine delay adders of the entire net structure in the customers application. pin assignments for the 256 mb ddr sdram planar component (top view) 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc nc nc nc v ddq nc nc v dd nc nc we cas ras cs nc ba0 ba1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc nc nc nc v ssq dqs nc v ref v ss dm clk clk cke nc a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss 64m x 4 x 4 bank
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 23 the table below describes the dq and cb wiring information for each sdram on the dimm. note that the dq wiring is different from that described in the block diagram. note: transmission lines (tl) are represented as cylinders and are labeled with length designators. these are the only lines which represent physical trace segments. for more detailed topology information please refer to the ddr sdram registered dimm design specification. sdram wiring information dq sdram designator dq sdram pin number device position to dimm tab i/o 1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 dq0 5 3 11 19 27 35 43 51 59 cb3 4 12 20 28 36 44 52 60 cb4 dq1 11 2 10182634425058cb25 13212937455361cb5 dq2 56 1 9 17 25 33 41 49 57 cb1 6 14 22 30 38 46 54 62 cb6 dq3 62 0 8 16 24 32 40 48 56 cb0 7 15 23 31 39 47 55 63 cb7 1. these numbers can be associated with the corresponding dimm tab pin by referencing the dimm connector pinout on pages 2 and 3 of this document. example: dq7 at the dimm tab (pin 99) is wired to sdram device position d9, pin 62. data, cb, dqs, and dm net structures trace lengths for data net structure tl0 tl1 total unit min max min max min max 0.13 0.19 0.95 1.02 1.13 1.15 inches tl0 dimm connector 22 w tl1 sdram pin
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 23 06k6597.h02812a 1/01 the table below describes the input wiring for each clock on the dimm. clock input wiring ck0, ck0 pll clk input pin 13, 14 clock topology trace lengths tl0 tl1 r1 [ohms] unit 1.00 0.20 120 inches tl0 ck0 ck0 phase locked loop (pll) tl1 r1 dimm connector
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 23 the table below describes the address and control information for each signal on the dimm. note: each signal has one register input load in order to aid in system level timings. register input wiring register pin number register 1 signal register 2 signal notes 25 nc a0 1 26 nc a10 1 29 cke0 ba1 30 a12 nc 1 31 a11 ba0 32 a9 ras 33 a7 we 40 a8 nc 1 41 a5 nc 1 42 a6 nc 1 43 a4 nc 1 44 a3 cas 47 a2 s0 48 a1 nc 1 1. register signals corresponding to nc inputs are tied to ground. address/control signal net structure trace lengths tl0 tl1 units min max min max 0.13 0.26 0.56 0.66 inches tl0 dimm connector tl1 register 22 w
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 23 06k6597.h02812a 1/01 functional description and timing diagrams refer to ibm 256mb synchronous ddr dram datasheet ( 29l0011.e36997a) for functional description and timing diagrams. refer to the ibm application note power up and power management on ddr rdimms for new ddr dimm features that facilitate controlled power up and minimize power consumption. note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design.
IBMB6M64734BGA preliminary 64mx72 one bank registered ddr sdram module 06k6597.h02812a 1/01 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 23 layout drawing for 64mx72 one bank registered dimm note: all dimensions are typical unless otherwise stated. detail a millimeters inches see detail a 1.7 43.33 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.80 front (2) 0 3.18 .1255 3.99 .157 max. side 1.27 0.10 .050 .004 4.24 .167 4.24 .167 (front) back 6.35 .250 1.80 .071 1.27 .050 3.80 .150 4.00 .157 1.00 .039 width pitch 10.0 .394 register 1 register 2 pll d0 d1 d2 d3 d8 d4 d5 d6 d7 d16 d15 d14 d13 d17 d12 d11 d10 d9
IBMB6M64734BGA 64mx72 one bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 23 06k6597.h02812a 1/01 revision log rev contents of modi?cation 3/00 initial release 1/01 upates to spec.
copyright and disclaimer ? copyright international business machines corporation 2000, 2001 all rights reserved printed in the united states of america january 2001 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warran- ties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com 06k6597.h02812a 1/01

▲Up To Search▲

Price & Availability of IBMB6M64734BGA

	To Download IBMB6M64734BGA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .